Jer-Min Jou

Publication Activity (10 Years)

Years Active: 1989-2014
Publications (10 Years): 0

Top Topics

Highly Efficient

Data Partitioning

Top Venues

Publications

Cheng-Hung Hsieh, Jer-Min Jou
A Run-time Manager for Multithreading of Multi-core Systems. ICS (2014)
Chun-Yu Chen, Yun-Lung Lee, Jer-Min Jou
A Transaction-based Design Model and Its MPEG-2 Encoder Design. ICS (2014)
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
Efficient design and generation of a multi-facet arbiter. SASP (2010)
Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. DAC (2010)
Jer-Min Jou, Yun-Lung Lee
An Optimal Round-Robin Arbiter Design for NoC. J. Inf. Sci. Eng. 26 (6) (2010)
Yun-Lung Lee, Jer-Min Jou, Yen-Yu Chen
A high-speed and decentralized arbiter design for NoC. AICCSA (2009)
Jer-Min Jou, Yun-Lung Lee, Chen-Yen Lin, Chien-Ming Sun
A Novel Reconfigurable Computation Unit for DSP Applications. ISVLSI (2007)
Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Yeu-Horng Shiau, Jer-Min Jou, Chin-Chi Liu
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme. IEICE Trans. Inf. Syst. (7) (2004)
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Pei-Yin Chen, Jer-Min Jou
An efficient blocking-matching algorithm based on fuzzy reasoning. IEEE Trans. Syst. Man Cybern. Part B 31 (2) (2001)
Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. ISCAS (2) (2001)
Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang
An efficient VLSI architecture for HMM-based speech recognition. ICECS (2001)
Pei-Yin Chen, Jer-Min Jou
Adaptive arithmetic coding using fuzzy reasoning and grey prediction. Fuzzy Sets Syst. 114 (2) (2000)
Jer-Min Jou, Pei-Yin Chen, Sheng-Fu Yang
An adaptive fuzzy logic controller: its VLSI architecture and applications. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun
A grey prediction motion estimator for digital image processing. ICECS (1999)
Jer-Min Jou, Pei-Yin Chen, Jian-Ming Sun
The gray prediction search algorithm for block motion estimation. IEEE Trans. Circuits Syst. Video Technol. 9 (6) (1999)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC (1999)
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau
A New Pipelined Architecture for Fuzzy Color Correction. ASP-DAC (1999)
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. ASP-DAC (1999)
Jer-Min Jou, Pei-Yin Chen
A fast and efficient lossless data-compression method. IEEE Trans. Commun. 47 (9) (1999)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS (1999)
Shung-Chih Chen, Jer-Min Jou
Diagnostic fault simulation for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (3) (1997)
Shung-Chih Chen, Jer-Min Jou
Serial diagnostic fault simulation for synchronous sequential circuits. Integr. 23 (2) (1997)
Jer-Min Jou, Shung-Chih Chen
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning. ISCAS (1995)
Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. ISCAS (1994)
Jer-Min Jou, Shung-Chih Chen
A fast and memory-efficient diagnostic fault simulation for sequential circuits. ICCAD (1994)
Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS (1994)
Jer-Min Jou, Shiann-Rong Kuang
Library-Adaptively Integrated Data Path Synthesis for DSP Systems. ICCD (1993)
Jer-Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang
An Efficient VLSI Switch-Box Router. IEEE Des. Test Comput. 7 (4) (1990)
Jer-Min Jou, Jau-Yien Lee
A new 3-layer rectilinear area router with obstacle avoidance. Integr. 7 (1) (1989)