Yeu-Horng Shiau

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 5

Top Topics

Hierarchical Representation

High Dynamic Range

Hardware Design

Trajectories Of Moving Objects

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

J. Inf. Sci. Eng.

IEEE J. Emerg. Sel. Topics Circuits Syst.

Publications

Cheng-Han Li, Yeu-Horng Shiau
Retraction Note: FPGA logic design method based on multi resolution image real time acquisition system. Evol. Intell. 16 (2) (2023)
Yeu-Horng Shiau, Kuan-Yu Huang, Pei-Yin Chen, Cho-Yu Kuo
A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge. IEEE J. Emerg. Sel. Topics Circuits Syst. 11 (4) (2021)
Cheng-Han Li, Yeu-Horng Shiau
FPGA logic design method based on multi resolution image real time acquisition system. Evol. Intell. 12 (3) (2019)
Yeu-Horng Shiau, Yao-Tsung Kuo, Pei-Yin Chen, Feng-Yuan Hsu
VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications. IEEE Trans. Circuits Syst. Video Technol. 29 (1) (2019)
Pei-Yin Chen, Yao-Tsung Kuo, Shih-Hsiang Lin, Yeu-Horng Shiau
Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications. ISCAS (2018)
Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Shang-Yuan Li
A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications. IEEE Trans. Intell. Transp. Syst. 16 (2) (2015)
Pei-Yin Chen, Yeu-Horng Shiau, Hung-Yu Yang, Wan-Yu Jhuang
A Weighted Edge-Preserving Smooth Filter for High Dynamic Range Image Display. J. Inf. Sci. Eng. 31 (3) (2015)
Yeu-Horng Shiau, Cheng-Han Li, Zhi-hao Wang, Yi Tai Guo
Hardware and Software Co-design of the Moving Object Tracking System. IIH-MSP (2014)
Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Ya-Zhu Chuang
Hardware Implementation of a Fast and Efficient Haze Removal Method. IEEE Trans. Circuits Syst. Video Technol. 23 (8) (2013)
Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Shi-Gi Huang
Power-efficient decoder implementation based on state transparent convolutional codes. IET Circuits Devices Syst. 6 (4) (2012)
Yeu-Horng Shiau, Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang
High Dynamic Range Image Rendering with Order-Statistics Filter. ICGEC (2012)
Hung-Yu Yang, Pei-Yin Chen, Chien-Chuan Huang, Ya-Zhu Chuang, Yeu-Horng Shiau
Low Complexity Underwater Image Enhancement Based on Dark Channel Prior. IBICA (2011)
Pei-Yin Chen, Chien-Chuan Huang, Yeu-Horng Shiau, Yao-Tung Chen
A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images. IEEE Trans. Circuits Syst. II Express Briefs (1) (2009)
Yeu-Horng Shiau, Jer-Min Jou, Chin-Chi Liu
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme. IEICE Trans. Inf. Syst. (7) (2004)
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. ISCAS (2) (2001)
Jer-Min Jou, Yeu-Horng Shiau, Chen-Jen Huang
An efficient VLSI architecture for HMM-based speech recognition. ICECS (2001)
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Jian-Ming Sun
A grey prediction motion estimator for digital image processing. ICECS (1999)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC (1999)
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau
A New Pipelined Architecture for Fuzzy Color Correction. ASP-DAC (1999)
Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. ASP-DAC (1999)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS (1999)