Ren-Der Chen

Publication Activity (10 Years)

Years Active: 1994-2021
Publications (10 Years): 2

Top Topics

Efficient Implementation

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Wei-Ting Chen, Ren-Der Chen, Pei-Yin Chen, Yu-Che Hsiao
A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (4) (2021)
Ren-Der Chen, Pei-Yin Chen, Chun-Hsien Yeh
A Low-Power Architecture for the Design of a One-Dimensional Median Filter. IEEE Trans. Circuits Syst. II Express Briefs (3) (2015)
Ren-Der Chen, Pei-Yin Chen, Chun-Hsien Yeh
Design of an Area-Efficient One-Dimensional Median Filter. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Pei-Yin Chen, Ren-Der Chen, Yu-Pin Chang, Leang-San Shieh, Heidar A. Malki
Hardware Implementation for a Genetic Algorithm. IEEE Trans. Instrum. Meas. 57 (4) (2008)
Pei-Yin Chen, Ren-Der Chen
An index coding algorithm for image vector quantization. IEEE Trans. Consumer Electron. 49 (4) (2003)
Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen
Design of a dynamic pipelined architecture for fuzzy color correction. IEEE Trans. Very Large Scale Integr. Syst. 10 (6) (2002)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ASP-DAC (1999)
Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau
An efficient method for the decomposition and resynthesis of speed-independent circuits. ICECS (1999)
Jer-Min Jou, Shung-Chih Chen, Ren-Der Chen
A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits. ISCAS (1994)
Jer-Min Jou, Ren-Der Chen, Shiann-Rong Kuang
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization. ISCAS (1994)