A Low-Power Architecture for the Design of a One-Dimensional Median Filter.
Ren-Der ChenPei-Yin ChenChun-Hsien YehPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2015)
Keyphrases
- low power
- vlsi architecture
- median filter
- low cost
- single chip
- power consumption
- high speed
- cmos technology
- low power consumption
- mixed signal
- nm technology
- digital signal processing
- vlsi implementation
- logic circuits
- power dissipation
- real time
- gate array
- ultra low power
- design considerations
- cmos image sensor
- median filtering
- vlsi circuits
- power reduction
- design methodology
- efficient implementation