Sih-Sian Wu

Publication Activity (10 Years)

Years Active: 2010-2021
Publications (10 Years): 13

Top Topics

Stereo Algorithm

Disparity Range

Stereo Matching

Belief Propagation

Top Venues

IEEE Trans. Circuits Syst. Video Technol.

Publications

Sih-Sian Wu, Liang-Gee Chen
CMWMF: Constant Memory Architecture of Weighted Mode/Median Filter for Extremely Large Label Depth Refinement. IEEE Trans. Circuits Syst. Video Technol. 31 (8) (2021)
Yu-Sheng Wu, Sih-Sian Wu, Tan Huang, Liang-Gee Chen
Online Training Refinement Network and Architecture Design for Stereo Matching. ISCAS (2021)
Sih-Sian Wu, Hon-Hui Chen, Liang-Gee Chen
Hardware- and Memory-Efficient Architecture for Disparity Estimation of Large Label Counts. IEEE Trans. Circuits Syst. Video Technol. 31 (9) (2021)
Tan Huang, Sih-Sian Wu, Jan Klopp, Po-Hsiang Yu, Liang-Gee Chen
A Computational Efficient Architecture for Extremely Sparse Stereo Network. ISCAS (2021)
Po-Hsiang Yu, Sih-Sian Wu, Liang-Gee Chen
KCP: Kernel Cluster Pruning for Dense Labeling Neural Networks. CoRR (2021)
Po-Hsiang Yu, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen, Shao-Yi Chien
Joint Pruning & Quantization for Extremely Sparse Neural Networks. CoRR (2020)
Chung-Yan Chih, Sih-Sian Wu, Jan P. Klopp, Liang-Gee Chen
Accurate and Bandwidth Efficient Architecture for CNN-based Full-HD Super-Resolution. ISCAS (2018)
Hsin-Yu Hou, Sih-Sian Wu, Da-Fang Chang, Liang-Gee Chen
Video Stereo Matching with Temporally Consistent Belief Propagation. ICME (2018)
Da-Fang Chang, Sih-Sian Wu, Hsin-Yu Hou, Liang-Gee Chen
Accurate and fast segment-based cost aggregation algorithm for stereo matching. MMSP (2017)
Sih-Sian Wu, Chen-Han Tsai, Liang-Gee Chen
Efficient Hardware Architecture for Large Disparity Range Stereo Matching Based on Belief Propagation. SiPS (2016)
Yi-Ting Shen, Guan-Lin Liu, Sih-Sian Wu, Liang-Gee Chen
3-D perception enhancement in autostereoscopic TV by depth cue for 3-D model interaction. ICCE (2016)
Sih-Sian Wu, Hong-Hui Chen, Chen-Han Tsai, Liang-Gee Chen
Memory efficient architecture for belief propagation based disparity estimation. ISCAS (2015)
Hong-Hui Chen, Chao-Tsung Huang, Sih-Sian Wu, Chia-Liang Hung, Tsung-Chuan Ma, Liang-Gee Chen
23.2 A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications. ISSCC (2015)
Sih-Sian Wu, Kanwen Wang, Sai Manoj Pudukotai Dinakarrao, Tsung-Yi Ho, Mingbin Yu, Hao Yu
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os. DATE (2014)
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (8) (2011)
Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu
Efficient design and generation of a multi-facet arbiter. SASP (2010)
Jer-Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang
New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model. DAC (2010)