Hsin-Shu Chen

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 15

Top Topics

Open Archives Initiative

Analog To Digital Converter

Synthetic Aperture Radar

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jun-Yi Wu, Hsin-Shu Chen
A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback. MWSCAS (2023)
Chi-Wei Chen, Chien-Yu Su, Hsin-Shu Chen
A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC. ISCAS (2022)
Tun-Yen Liao, Hsin-Shu Chen, Wen-Jong Wu
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques. ISCAS (2021)
Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, Shih-Wei Wu
A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration. ISCAS (2020)
Chi-Wei Chen, Hsin-Shu Chen, Wen-Jong Wu
A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique. MWSCAS (2019)
Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen
A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. IEEE J. Solid State Circuits 54 (10) (2019)
Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart, Wen-Jong Wu
A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting. ISCAS (2018)
Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, Hsin-Shu Chen
An 89.55dB-SFDR 179.6dB-FoMs 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration. A-SSCC (2018)
Yao-Sheng Hu, Li-Yu Huang, Hsin-Shu Chen
A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System. A-SSCC (2018)
Hsin-Shu Chen, Jia-Nan Tai, Yi-Jan Emery Chen, Jau-Horng Chen
A current average control method for transient-glitch reduction in variable frequency DC-DC converters. ISCAS (2017)
Yao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen
A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique. A-SSCC (2016)
Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, Hsin-Shu Chen
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs (12) (2016)
Yao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen
A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC. A-SSCC (2016)
Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, Hsin-Shu Chen
An 8-bit 900MS/S two-step SAR ADC. ISCAS (2016)
Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, Hsin-Shu Chen
An 8 b 700 MS/s 1 b/Cycle SAR ADC Using a Delay-Shift Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2016)
Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen
A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (5) (2014)
Chien-Jian Tseng, Chieh-Fan Lai, Hsin-Shu Chen
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2014)
Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS. A-SSCC (2014)
Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. ISSCC (2014)
Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, Hsin-Shu Chen
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2013)
Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, Hsin-Shu Chen
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC. IEEE J. Solid State Circuits 47 (6) (2012)
Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS. VLSIC (2012)
Jia-Nan Tai, Hsin-Shu Chen, Hang-Quei Chiu
A highly integrated class-D amplifier using driver delay hysteresis control. VLSI-DAT (2012)
Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, Yi-Jan Emery Chen
A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2012)
Hsin-Shu Chen, Jyun-Cheng Lin
A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop. IEICE Trans. Electron. (6) (2010)
Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, Hsin-Shu Chen
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS. IEEE J. Solid State Circuits 44 (11) (2009)
Sen-Wen Hsiao, Yen-Chih Huang, David Liang, H.-W. K. Chen, Hsin-Shu Chen
A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming. ISCAS (2006)
Hsin-Shu Chen, Bang-Sup Song, Kantilal Bacrania
A 14-b 20-Msamples/s CMOS pipelined ADC. IEEE J. Solid State Circuits 36 (6) (2001)
Hsin-Shu Chen, A. Ito
Characterization of 1/f noise vs. number of gate stripes in MOS transistors. ISCAS (2) (1999)