A 14-b 20-Msamples/s CMOS pipelined ADC.

Hsin-Shu Chen Bang-Sup Song Kantilal Bacrania

Published in: IEEE J. Solid State Circuits (2001)

Keyphrases

analog to digital converter
single chip
high speed
analog vlsi
power consumption
low cost
circuit design
image sensor
data flow
delay insensitive
low power
vlsi circuits
cmos image sensor
low voltage
real time
rolling shutter
sigma delta
wide dynamic range
parallel processing