A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS.

Yao-Sheng Hu Chi-Huai Shih Hung-Yen Tai Hung-Wei Chen Hsin-Shu Chen

Published in: A-SSCC (2014)

Keyphrases

analog to digital converter
power consumption
random access memory
nm technology
high speed
parameter estimation
successive approximation
synthetic aperture radar
image sensor
multiscale
multiresolution
post processing
sar images
cmos technology