11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS.

Hung-Yen Tai Yao-Sheng Hu Hung-Wei Chen Hsin-Shu Chen

Published in: ISSCC (2014)

Keyphrases

high speed
cmos technology
post processing
power consumption
low power
synthetic aperture radar
single chip
low cost
sar images
analog vlsi
silicon on insulator
multiresolution
parameter estimation