A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop.

Hsin-Shu Chen Jyun-Cheng Lin

Published in: IEICE Trans. Electron. (2010)

Keyphrases

low power
mixed signal
power consumption
power dissipation
low cost
high speed
vlsi circuits
high power
single chip
wireless transmission
multi channel
cmos technology
digital signal processing
gate array
low power consumption
vlsi architecture
logic circuits
cmos image sensor
image sensor
signal processor