Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement.
Chin-Long WeyMohammad Athar KhalilJim LiuGregory WierzbaPublished in: ACM Great Lakes Symposium on VLSI (2004)
Keyphrases
- gate dielectrics
- electrical properties
- silicon dioxide
- low voltage
- field effect transistors
- leakage current
- analog vlsi
- power supply
- si sio
- cmos technology
- circuit design
- room temperature
- cmos image sensor
- power system
- steady state
- focal plane
- neural network
- image processing
- low cost
- high speed
- signal processing
- mixed signal
- contrast enhancement
- low power
- x ray
- electron microscopy
- image sensor
- high density
- computational intelligence
- metal oxide
- power consumption
- image enhancement