Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates.
Sajjad ParvinMustafa AltunPublished in: IEEE Access (2019)
Keyphrases
- logic circuits
- fault detection
- low power
- power consumption
- high speed
- low cost
- power dissipation
- fault diagnosis
- fault identification
- industrial processes
- tennessee eastman
- functional decomposition
- gate array
- tunnel diode
- fault isolation
- fault localization
- failure detection
- condition monitoring
- error correction
- fault detection and diagnosis
- logic synthesis
- fuel cell
- pattern recognition
- fault detection and isolation
- digital signal processing
- robust fault detection
- decision making
- neural network