Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.
Hikaru TamuraKiyoshi KatoTakahiko IshizuTatsuya OnukiWataru UesugiTakuro OhmaruKazuaki OhshimaHidetomo KobayashiSeiichi YonedaAtsuo IsobeNaoaki TsutsuiSuguru HondoYasutaka SuzukiYutaka OkazakiTomoaki AtsumiYutaka ShionoiriYukio MaehashiGensuke GotoMasahiro FujitaJames MyersPekka KorpinenJun KoyamaYoshitaka YamamotoShunpei YamazakiPublished in: COOL Chips (2014)
Keyphrases
- transmission electron microscopy
- power consumption
- leakage current
- power reduction
- cmos technology
- silicon dioxide
- low voltage
- power dissipation
- dynamic random access memory
- x ray
- clock gating
- low power
- room temperature
- power management
- power saving
- ibm power processor
- random access memory
- chip design
- field effect transistors
- nm technology
- high resolution
- electrical properties
- high speed
- information processing
- embedded systems
- silicon on insulator
- metal oxide
- data center
- memory subsystem
- human brain
- semiconductor manufacturing
- fuel cell
- electron microscopy
- analog circuits
- power line
- design considerations
- visual cortex
- high temperature
- low cost