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Yusuke Tokunaga
Publication Activity (10 Years)
Years Active: 1999-2014
Publications (10 Years): 0
Top Topics
Recognition Algorithm
Delta Sigma Modulators
Convex Hull
Simulated Annealing
Top Venues
BWCCA
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
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Publications
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Ningping Sun
,
Yusuke Tokunaga
An Alternative Flocking Algorithm with Additional Dynamic Conditions.
BWCCA
(2014)
Koji Obata
,
Kazuo Matsukawa
,
Yosuke Mitani
,
Masao Takayama
,
Yusuke Tokunaga
,
Shiro Sakiyama
,
Shiro Dosho
A Low Distortion 3rd-Order Continuous-Time Delta-Sigma Modulator for a Worldwide Digital TV-Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(2) (2012)
Yusuke Tokunaga
,
Shiro Sakiyama
,
Akinori Matsumoto
,
Shiro Dosho
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.
IEEE J. Solid State Circuits
45 (6) (2010)
Kazuo Matsukawa
,
Yosuke Mitani
,
Masao Takayama
,
Koji Obata
,
Yusuke Tokunaga
,
Shiro Sakiyama
,
Shiro Dosho
-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver.
CICC
(2010)
Kazuo Matsukawa
,
Takashi Morie
,
Yusuke Tokunaga
,
Shiro Sakiyama
,
Yosuke Mitani
,
Masao Takayama
,
Takuji Miki
,
Akinori Matsumoto
,
Koji Obata
,
Shiro Dosho
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
ASP-DAC
(2009)
Yusuke Tokunaga
,
Shiro Sakiyama
,
Akinori Matsumoto
,
Shiro Dosho
An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.
ISSCC
(2009)
Akinori Matsumoto
,
Shiro Sakiyama
,
Yusuke Tokunaga
,
Takashi Morie
,
Shiro Dosho
A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System.
IEEE J. Solid State Circuits
43 (4) (2008)
Yusuke Tokunaga
,
Shiro Sakiyama
,
Shiro Dosho
,
Yasuyuki Doi
,
Makoto Hattori
9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface.
ISSCC
(2006)
Shiro Dosho
,
Shiro Sakiyama
,
Noriaki Takeda
,
Yusuke Tokunaga
,
Takashi Morie
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution.
ISSCC
(2006)
Yusuke Tokunaga
,
Toshihide Hakukawa
,
Takahiro Inoue
Algorithm and Design of an Intelligent Digital Integrated Circuit for a Watermelon Harvesting Robot.
J. Robotics Mechatronics
11 (3) (1999)