An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage.
Yusuke TokunagaShiro SakiyamaAkinori MatsumotoShiro DoshoPublished in: ISSCC (2009)
Keyphrases
- chip design
- power consumption
- analog vlsi
- power dissipation
- high speed
- low cost
- ibm power processor
- silicon on insulator
- low power
- cmos technology
- circuit design
- ultra low power
- nm technology
- feedback loop
- cmos image sensor
- single chip
- image sensor
- mixed signal
- multithreading
- power management
- focal plane
- programmable logic
- probabilistic relaxation
- low power consumption
- vlsi circuits
- physical design
- energy efficiency
- random access memory
- inversely proportional
- solid state
- iterative algorithms
- memory subsystem
- semidefinite
- differential equations
- digital camera