Usha Sandeep Mehta

Publication Activity (10 Years)

Years Active: 2009-2018
Publications (10 Years): 2

Top Topics

Cmos Technology

Design Considerations

Top Venues

IET Comput. Digit. Tech.

J. Electron. Test.

Publications

Vaishali H. Dhare, Usha Sandeep Mehta
Multiple Missing Cell Defect Modeling for QCA Devices. J. Electron. Test. 34 (6) (2018)
Mark Zwolinski, Manoj Singh Gaur, Vijay Laxmi, Usha Sandeep Mehta
Guest Editorial. IET Comput. Digit. Tech. 10 (5) (2016)
Rakesh Trivedi, N. M. Devashrayee, Usha Sandeep Mehta, N. M. Desai, Himanshu Patel
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology. VDAT (2015)
Harikrishna Parmar, Usha Sandeep Mehta
A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC. VDAT (2015)
Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method. VLSI Design 2011 (2011)
Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey. VLSI Design 2011 (2011)
Kinjal A. Bhavsar, Usha Sandeep Mehta
Analysis of test data compression techniques emphasizing statistical coding schemes. ICWET (2011)
Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead. J. Electron. Test. 26 (6) (2010)
Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta
Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead. ISVLSI (2010)
Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta
Hamming Distance Based 2-D Reordering with Power Efficient Don't Care Bit Filling: Optimizing the test data compression method. SoC (2010)
Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee
Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. VLSI Design (2010)
Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee
Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds? - A Survey. VLSI Design 2010 (2010)
Usha Sandeep Mehta, Kankar S. Dasgupta, Niranjan M. Devashrayee
Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead. APCCAS (2010)
Usha Sandeep Mehta, Kankar S. Dasgupta, Nirnjan M. Devashrayee
Survey of Test Data Compression Technique Emphasizing Code Based Schemes. DSD (2009)