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N. M. Devashrayee
ORCID
Publication Activity (10 Years)
Years Active: 2009-2018
Publications (10 Years): 1
Top Topics
Cmos Technology
Logic Circuits
Wireless Transmission
Power Dissipation
Top Venues
VDAT
Microelectron. J.
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Publications
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Vijay Savani
,
N. M. Devashrayee
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.
Microelectron. J.
74 (2018)
Rakesh Trivedi
,
N. M. Devashrayee
,
Usha Sandeep Mehta
,
N. M. Desai
,
Himanshu Patel
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology.
VDAT
(2015)
Vijay Savani
,
N. M. Devashrayee
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.
VDAT
(2015)
A. P. Naik
,
N. M. Devashrayee
A novel OTA and FVF based second generation current conveyor.
ICWET
(2011)
Shruti Oza
,
N. M. Devashrayee
Low voltage, high folding rate folding amplifier.
ICWET
(2010)
Shruti Oza
,
N. M. Devashrayee
Low Voltage, Low Power Folding Amplifier for Folding & Interpolating ADC.
ARTCom
(2009)