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Vijay Savani
ORCID
Publication Activity (10 Years)
Years Active: 2015-2024
Publications (10 Years): 2
Top Topics
Logic Circuits
Low Power Consumption
Nm Technology
Digital Signal Processing
Top Venues
Microelectron. J.
VDAT
J. Circuits Syst. Comput.
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Publications
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Parthiv Bhau
,
Vijay Savani
Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders.
J. Circuits Syst. Comput.
33 (1) (2024)
Vijay Savani
,
N. M. Devashrayee
Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator.
Microelectron. J.
74 (2018)
Vijay Savani
,
N. M. Devashrayee
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology.
VDAT
(2015)