Soumitra Bose

Publication Activity (10 Years)

Years Active: 1988-2007
Publications (10 Years): 0

Publications

Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal
Delay fault simulation with bounded gate delay mode. ITC (2007)
Soumitra Bose, Vishwani D. Agrawal
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC (2007)
Soumitra Bose, Vishwani D. Agrawal
Delay Test Quality Evaluation Using Bounded Gate Delays. VTS (2007)
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS (2006)
Soumitra Bose, Vishwani D. Agrawal
Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC (2006)
Soumitra Bose, Amit Nandi
Schematic array models for associative and non-associative memory circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Soumitra Bose, Amit Nandi
Extraction of Schematic Array Models for Memory Circuits. DATE (2004)
Soumitra Bose
Modeling Custom Digital Circuits for Test. J. Electron. Test. 20 (6) (2004)
Soumitra Bose
Automated Modeling of Custom Digital Circuits for Test. DATE (2002)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47 (8) (1998)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
A rated-clock test method for path delay faults. IEEE Trans. Very Large Scale Integr. Syst. 6 (2) (1998)
Soumitra Bose, Prathima Agrawal
Concurrent fault simulation on message passing multicomputers. IEEE Trans. Very Large Scale Integr. Syst. 6 (2) (1998)
Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski
Algorithms for Switch Level Delay Fault Simulation. ITC (1997)
Soumitra Bose, Vishwani D. Agrawal
Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium (1995)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Generation of Compact Delay Tests by Multiple-Path Activation. ITC (1993)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Logic systems for path delay test generation. EURO-DAC (1993)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Path delay fault simulation of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
A Path Delay Fault Simulator for Sequential Circuits. VLSI Design (1993)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
The optimistic update theorem for path delay testing in sequential circuits. J. Electron. Test. 4 (3) (1993)
Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal
Delay fault testability evaluation through timing simulation. Great Lakes Symposium on VLSI (1993)
Soumitra Bose, Prathima Agrawal
Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers. DAC (1992)
Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. J. Autom. Reason. 8 (2) (1992)
Soumitra Bose, Edmund M. Clarke, David E. Long, Spiro Michaylov
PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses LICS (1989)
Soumitra Bose, Allan L. Fisher
Verifying pipelined hardware using symbolic logic simulation. ICCD (1989)
P. E. Allen, Soumitra Bose, Edmund M. Clarke, Spiro Michaylov
PARTHENON: A Parallel Theorem Prover for Non-Horn Clauses. CADE (1988)