Shantanu Dutt

Publication Activity (10 Years)

Years Active: 1988-2022
Publications (10 Years): 6

Top Topics

Energy Minimization

High Level Synthesis

Scheduling Algorithm

Top Venues

J. Low Power Electron.

Publications

Xiuyan Zhang, Shantanu Dutt
Limiting Interconnect Heating in Power-Driven Physical Synthesis. SLIP (2022)
Shantanu Dutt, Xiuyan Zhang, Ouwen Shi
On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis. ISQED (2021)
Xiuyan Zhang, Ouwen Shi, Jian Xu, Shantanu Dutt
A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding. J. Low Power Electron. 15 (4) (2019)
Shantanu Dutt, Ouwen Shi
A fast and effective lookahead and fractional search based scheduling algorithm for high-level synthesis. DATE (2018)
Shantanu Dutt, Ouwen Shi
Power-delay product based resource library construction for effective power optimization in HLS. ISQED (2017)
Ouwen Shi, Shantanu Dutt
Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis. J. Low Power Electron. 12 (4) (2016)
Enzo Tartaglione, Shantanu Dutt
Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS Designs. ICCAD (2015)
Shantanu Dutt, Dinesh P. Mehta, Gi-Joon Nam
New Algorithmic Techniques for Complex EDA Problems. VLSI Design 2014 (2014)
Huan Ren, Shantanu Dutt
Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm. VLSI Design 2013 (2013)
Huan Ren, Shantanu Dutt
Assignments, Gate Sizing, and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (5) (2011)
Shantanu Dutt, Huan Ren
Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Huan Ren, Shantanu Dutt
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement. IEEE Trans. Very Large Scale Integr. Syst. 19 (7) (2011)
Shantanu Dutt, Huan Ren
Timing yield optimization via discrete gate sizing using globally-informed delay PDFs. ICCAD (2010)
Shantanu Dutt, Yang Dai, Huan Ren, Joel Fontanarosa
Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach. BICoB (2009)
Shantanu Dutt, Li Li
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures. ACM Trans. Reconfigurable Technol. Syst. 2 (1) (2009)
Huan Ren, Shantanu Dutt
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. ICCAD (2008)
Shantanu Dutt, Vinay Verma, Vishal Suthar
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (2) (2008)
Huan Ren, Shantanu Dutt
Constraint satisfaction in incremental placement with application to performance optimization under power constraints. ICCD (2007)
Nihar R. Mahapatra, Shantanu Dutt
An efficient delay-optimal distributed termination detection algorithm. J. Parallel Distributed Comput. 67 (10) (2007)
Shantanu Dutt, Hasan Arslan
Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. DATE (2006)
Vishal Suthar, Shantanu Dutt
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. DATE (2006)
Federico Rota, Shantanu Dutt, Sahithi Krishna
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. DFT (2006)
Vishal Suthar, Shantanu Dutt
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. VTS (2006)
Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar
A network-flow approach to timing-driven incremental placement for ASICs. ICCAD (2006)
Vishal Suthar, Shantanu Dutt
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ACM Great Lakes Symposium on VLSI (2005)
Hasan Arslan, Shantanu Dutt
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. ACM Great Lakes Symposium on VLSI (2004)
Vinay Verma, Shantanu Dutt
Roving testing using new built-in-self-tester designs for FPGAs. FPGA (2004)
Hasan Arslan, Shantanu Dutt
A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. ICCD (2004)
Nihar R. Mahapatra, Shantanu Dutt
Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. Parallel Comput. 30 (5-6) (2004)
Vinay Verma, Shantanu Dutt, Vishal Suthar
Efficient on-line testing of FPGAs with provable diagnosabilities. DAC (2004)
Hasan Arslan, Shantanu Dutt
ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. ICCD (2003)
Shantanu Dutt, Wenyong Deng
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Ke Zhong, Shantanu Dutt
Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. DAC (2002)
Shantanu Dutt, Vinay Verma, Hasan Arslan
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. ACM Trans. Design Autom. Electr. Syst. 7 (4) (2002)
Nihar R. Mahapatra, Shantanu Dutt
Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. J. Parallel Distributed Comput. 61 (10) (2001)
Vinay Verma, Shantanu Dutt
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. ICCAD (2001)
Shantanu Dutt, Wenyong Deng
Probability-based approaches to VLSI circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (5) (2000)
Ke Zhong, Shantanu Dutt
Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. ICCAD (2000)
Nihar R. Mahapatra, Shantanu Dutt
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. Int. J. Found. Comput. Sci. 11 (2) (2000)
Shantanu Dutt, Hasan Arslan, Halim Theny
Partitioning using second-order information and stochastic-gainfunctions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Nihar R. Mahapatra, Shantanu Dutt
Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. FTCS (1999)
Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. ICCAD (1999)
Shantanu Dutt, Halim Theny
Partitioning using second-order information and stochastic-gain functions. ISPD (1998)
Nihar R. Mahapatra, Shantanu Dutt
Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. IPPS/SPDP (1998)
Fran Hanchek, Shantanu Dutt
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. IEEE Trans. Computers 47 (1) (1998)
Nihar R. Mahapatra, Shantanu Dutt
Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. IEEE Trans. Parallel Distributed Syst. 8 (7) (1997)
Shantanu Dutt, Fran Hanchek
REMOD: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 5 (1) (1997)
Shantanu Dutt, Halim Theny
Partitioning around roadblocks: tackling constraints with intermediate relaxations. ICCAD (1997)
Shantanu Dutt, Nihar R. Mahapatra
Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. IEEE Trans. Computers 46 (9) (1997)
Nihar R. Mahapatra, Shantanu Dutt
Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. FTCS (1996)
Fran Hancheck, Shantanu Dutt
Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. ICCD (1996)
Nihar R. Mahapatra, Shantanu Dutt
Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. IPPS (1996)
Shantanu Dutt, Nam Trinh
-Cubes for the Class of Parallel Divide-and-Conquer Algorithms. International Conference on Supercomputing (1996)
Shantanu Dutt, Wenyong Deng
VLSI circuit partitioning by cluster-removal using iterative improvement techniques. ICCAD (1996)
Shantanu Dutt, Wenyong Deng
A Probability-Based Approach to VLSI Circuit Partitioning. DAC (1996)
Fran Hanchek, Shantanu Dutt
Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. VLSI Design (1996)
Shantanu Dutt, Fikri T. Assaad
Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations. IEEE Trans. Computers 45 (4) (1996)
Shantanu Dutt, Nihar R. Mahapatra
Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. FTCS (1995)
Nihar R. Mahapatra, Shantanu Dutt
New Anticipatory Load Balancing Strategies for Parallel A* Algorithms. Parallel Processing of Discrete Optimization Problems (1994)
Shantanu Dutt, Nihar R. Mahapatra
Scalable Load Balancing Strategies for Parallel A* Algorithms. J. Parallel Distributed Comput. 22 (3) (1994)
Shantanu Dutt, Nihar R. Mahapatra
Algorithms and Their Performance on Hypercube Multiprocessors. IPPS (1993)
Shantanu Dutt
Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors. SPDP (1993)
Shantanu Dutt
New faster Kernighan-Lin-type graph-partitioning algorithms. ICCAD (1993)
Nihar R. Mahapatra, Shantanu Dutt
Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. SPDP (1993)
Shantanu Dutt, John P. Hayes
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. IEEE Trans. Computers 41 (5) (1992)
Fikri T. Assaad, Shantanu Dutt
More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication. FTCS (1992)
Shantanu Dutt, John P. Hayes
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. FTCS (1991)
Shantanu Dutt, John P. Hayes
Subcube Allocation in Hypercube Computers. IEEE Trans. Computers 40 (3) (1991)
Shantanu Dutt, John P. Hayes
Designing Fault-Tolerant System Using Automorphisms. J. Parallel Distributed Comput. 12 (3) (1991)
Shantanu Dutt, John P. Hayes
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. IEEE Trans. Computers 39 (4) (1990)
Shantanu Dutt, John P. Hayes
An automorphic approach to the design of fault-tolerant multiprocessors. FTCS (1989)
Shantanu Dutt, John P. Hayes
On allocating subcubes in a hypercube multiprocessor. C³P (1988)
Shantanu Dutt, John P. Hayes
Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures. FTCS (1988)