Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream.
Federico RotaShantanu DuttSahithi KrishnaPublished in: DFT (2006)
Keyphrases
- memory hierarchy
- memory access
- control flow
- processor core
- memory subsystem
- high speed
- instruction set
- single chip
- level parallelism
- multithreading
- cache misses
- ibm power processor
- data flow
- main memory
- random access memory
- operating system
- computing power
- data access
- speculative execution
- computer architecture
- functional verification
- memory management
- memory bandwidth
- ibm zenterprise
- database operations
- secondary storage
- access patterns
- shared memory
- prefetching
- software testing
- workflow management systems