Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays.
Nihar R. MahapatraShantanu DuttPublished in: J. Parallel Distributed Comput. (2001)
Keyphrases
- fault tolerant
- fault tolerance
- distributed systems
- mesh connected
- low cost
- interconnection networks
- hardware implementation
- massively parallel
- load balancing
- array processor
- state machine
- parallel computing
- evolvable hardware
- safety critical
- parallel architectures
- field programmable gate array
- image processing
- routing algorithm
- response time