Seiya Tanikawa

Publication Activity (10 Years)

Years Active: 2013-2015
Publications (10 Years): 2

Top Topics

Integrated Circuit

Evaluation Method

Top Venues

Publications

Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka
Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. 3DIC (2015)
Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka
Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. 3DIC (2015)
Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC (2013)