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Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC.

Hisashi KinoHideto HashiguchiSeiya TanikawaYohei SugawaraShunsuke IkegayaTakafumi FukushimaMitsumasa KoyanagiTetsu Tanaka
Published in: 3DIC (2015)
Keyphrases
  • integrated circuit
  • artificial neural networks
  • data reduction
  • layout design
  • artificial intelligence
  • feature selection
  • knowledge base