Min-Jae Seo

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 17

Top Topics

Binary Representation

Cmos Technology

Delta Sigma Modulators

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits 59 (8) (2024)
Sun-A Jo, Ji-Won Seo, Min-Jae Seo
A Hardware-efficient Rate Encoding Hardware with Latch-based TRNG. ICEIC (2024)
Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, Seung-Tak Ryu
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. CICC (2023)
Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. IEEE J. Solid State Circuits 57 (9) (2022)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Seung-Tak Ryu
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits 55 (10) (2020)
Dong-Shin Jo, Ba-Ro-Saim Sung, Min-Jae Seo, Woo-Cheol Kim, Seung-Tak Ryu
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. IEEE Trans. Circuits Syst. II Express Briefs (4) (2020)
Jongpal Kim, Wonseok Lee, Junyeub Suh, Hyungwoo Lee, Kyu-Il Lee, Ho Young Ahn, Min-Jae Seo, Seung-Tak Ryu, Kirill Y. Aristovich, David S. Holder, Sang Joon Kim
A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section. EMBC (2020)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC (2019)
Min-Jae Seo, Ye-Dam Kim, Jae-Hyun Chung, Seung-Tak Ryu
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. VLSI Circuits (2019)
Dong-Hwan Jin, Ji-Wook Kwon, Min-Jae Seo, Mi-Young Kim, Min-Chul Shin, Seokjoon Kang, Junghyuk Yoon, Taek-Seung Kim, Seung-Tak Ryu
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. IEEE J. Solid State Circuits 54 (6) (2019)
Si-Nai Kim, Woo-Cheol Kim, Min-Jae Seo, Seung-Tak Ryu
A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs. IEEE Trans. Circuits Syst. II Express Briefs (9) (2018)
Dong-Jin Chang, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. IEEE Trans. Circuits Syst. II Express Briefs (3) (2018)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)
Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits 53 (4) (2018)
Dong-Jin Chang, Wan Kim, Min-Jae Seo, Hyeok-Ki Hong, Seung-Tak Ryu
Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits 51 (8) (2016)
Dong-Ryeol Oh, Jong-In Kim, Min-Jae Seo, Jin-Gwang Kim, Seung-Tak Ryu
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. ESSCIRC (2015)