Ye-Dam Kim

Publication Activity (10 Years)

Years Active: 2018-2024
Publications (10 Years): 13

Top Topics

Signal Acquisition

Synthetic Aperture Radar

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits 59 (8) (2024)
Jae-Hyun Chung, Ye-Dam Kim, Chang-Un Park, Kun-Woo Park, Min-Jae Seo, Seung-Tak Ryu
An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. CICC (2023)
Kent Edrian Lozada, Dong-Hun Lee, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu
-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC (2023)
Kent Edrian Lozada, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu
-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. IEEE J. Solid State Circuits 56 (4) (2021)
Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Dong-Jin Chang, Seung-Tak Ryu
A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. A-SSCC (2021)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Seung-Tak Ryu
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. IEEE J. Solid State Circuits 55 (10) (2020)
Dong-Ryeol Oh, Kyoung-Jun Moon, Won-Mook Lim, Ye-Dam Kim, Eun-Ji An, Seung-Tak Ryu
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. VLSI Circuits (2020)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Jong-Pal Kim, Dong-Jin Chang, Won-Mook Lim, Jae-Hyun Chung, Chang-Un Park, Eun-Ji An, Seung-Tak Ryu
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. A-SSCC (2019)
Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim, Seung-Tak Ryu
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. VLSI Circuits (2019)
Min-Jae Seo, Ye-Dam Kim, Jae-Hyun Chung, Seung-Tak Ryu
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. VLSI Circuits (2019)
Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Min-Jae Seo, Yi-Ju Roh, Dong-Jin Chang, Wan Kim, Ye-Dam Kim, Seung-Tak Ryu
A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. IEEE Trans. Circuits Syst. II Express Briefs (12) (2018)