A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC.

Min-Jae Seo Ye-Dam Kim Jae-Hyun Chung Seung-Tak Ryu

Published in: VLSI Circuits (2019)

Keyphrases

single chip
image processing
multiscale
low cost
image reconstruction
dynamic range
cmos technology
analog to digital converter