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Il-Hoon Jang
ORCID
Publication Activity (10 Years)
Years Active: 2015-2022
Publications (10 Years): 4
Top Topics
Delta Sigma
Incremental Version
Analog To Digital Converter
Noise Shaping
Top Venues
ISSCC
IEEE Trans. Circuits Syst. II Express Briefs
MWSCAS
IEEE J. Solid State Circuits
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Publications
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Kent Edrian Lozada
,
Il-Hoon Jang
,
Gyeom-Je Bae
,
Dong-Hun Lee
,
Ye-Dam Kim
,
Hankyu Lee
,
Seong Joong Kim
,
Seung-Tak Ryu
-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling.
IEEE Trans. Circuits Syst. II Express Briefs
69 (9) (2022)
Seung-Yeob Baek
,
Il-Hoon Jang
,
Michael Choi
,
Hyungdong Roh
,
Woongtaek Lim
,
Youngjae Cho
,
Jongshin Shin
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET.
ISSCC
(2021)
Il-Hoon Jang
,
Min-Jae Seo
,
Sang-Hyun Cho
,
Jae-Keun Lee
,
Seung-Yeob Baek
,
Sunwoo Kwon
,
Michael Choi
,
Hyung-Jong Ko
,
Seung-Tak Ryu
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling.
IEEE J. Solid State Circuits
53 (4) (2018)
Ki-Hoon Seo
,
Il-Hoon Jang
,
Kyung-Jun Noh
,
Seung-Tak Ryu
An incremental zoom sturdy MASH ADC.
MWSCAS
(2017)
Ba-Ro-Saim Sung
,
Dong-Shin Jo
,
Il-Hoon Jang
,
Dong-Suk Lee
,
Yong-Sang You
,
Yong-Hee Lee
,
Ho-Jin Park
,
Seung-Tak Ryu
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS.
ISSCC
(2015)