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A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration.
Woo-Cheol Kim
Dong-Shin Jo
Yi-Ju Roh
Ye-Dam Kim
Seung-Tak Ryu
Published in:
VLSI Circuits (2019)
Keyphrases
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high speed
camera calibration
learning phase