A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration.
Dong-Jin ChangMin-Jae SeoHyeok-Ki HongSeung-Tak RyuPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
- low power
- cmos technology
- nm technology
- power dissipation
- high speed
- power consumption
- low cost
- low voltage
- single chip
- vlsi circuits
- clock frequency
- high power
- digital signal processing
- wireless transmission
- vlsi architecture
- low power consumption
- signal processor
- image sequences
- power reduction
- logic circuits
- power saving
- field programmable gate array
- real time