Michiaki Muraoka

Publication Activity (10 Years)

Years Active: 1982-2014
Publications (10 Years): 0

Top Topics

Correlation Analysis

Top Venues

Publications

Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga
A critical net reshape-router for high-performance VLSI layout design. APCCAS (2014)
Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga
A multilayer crosstalk avoidance router using restricted maze grids. MWSCAS (2013)
Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada
Design methodology for SoC arthitectures based on reusable virtual cores. ASP-DAC (2004)
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. IEICE Trans. Inf. Syst. (3) (2004)
Yoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki
VCore-based platform for SoC design. ASP-DAC (2003)
Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka
VCDS tool demonstration. ASP-DAC (2003)
Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. Asian Test Symposium (2003)
Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida
VCore-based design methodology. ASP-DAC (2003)
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
A DFT Selection Method for Reducing Test Application Time of System-on-Chips. Asian Test Symposium (2003)
Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada
Synthesis for SoC architecture using VCores. ASP-DAC (2003)
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits. VTS (2002)
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. Asian Test Symposium (2002)
Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
A SoC Test Strategy Based on a Non-Scan DFT Method. Asian Test Symposium (2002)
Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu
A Partial Scan Design Method Based on n-Fold Line-up Structures. Asian Test Symposium (1997)
Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka
A Design for testability Method Using RTL Partitioning. Asian Test Symposium (1996)
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
Design for testability using register-transfer level partial scan selection. ASP-DAC (1995)
Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin
A State Traversal Algorithm Using a State Covariance Matrix. DAC (1993)
Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa
ACTAS: an accurate timing analysis system for VLSI. DAC (1985)
Kazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka
Logic simulation for LSI. DAC (1982)