Juraj Brenkus

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 4

Top Topics

Calculation Method

Cmos Technology

Power Dissipation

Top Venues

Comput. Informatics

Microprocess. Microsystems

Microelectron. Reliab.

Publications

Miroslav Potocný, Juraj Brenkus, Viera Stopjaková
High side power MOSFET switch driver for a low-power AC/DC converter. DDECS (2019)
Juraj Brenkus, Viera Stopjaková, Viera Cernanová, Daniel Arbet, Lukás Nagy, Vladimír Sedlák
A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits. J. Circuits Syst. Comput. 26 (8) (2017)
Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Juraj Brenkus
Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology. DDECS (2016)
Juraj Brenkus, Viera Stopjaková, Lukás Nagy, Daniel Arbet
Impedance calculation based method for AC fault analysis of mixed-signal circuits. DDECS (2016)
Gábor Gyepes, Viera Stopjaková, Daniel Arbet, Libor Majer, Juraj Brenkus
test approach and its efficiency in covering resistive opens in SRAM arrays. Microprocess. Microsystems 38 (5) (2014)
Daniel Arbet, Viera Stopjaková, Juraj Brenkus, Gábor Gyepes, Martin Kovác, Libor Majer
BIST architecture for oscillation test of analog ICs and investigation of test hardware influence. Microelectron. Reliab. 54 (5) (2014)
Lukás Nagy, Viera Stopjaková, Juraj Brenkus
Current Sensing Completion Detection in Single-Rail Asynchronous Systems. Comput. Informatics 33 (5) (2014)
Juraj Brenkus, Viera Stopjaková, Daniel Arbet, Gábor Gyepes, Libor Majer
A novel impedance calculation method and its time efficiency evaluation. DDECS (2014)
Juraj Brenkus, Viera Stopjaková, Gábor Gyepes
Numerical method for DC fault analysis simplification and simulation time reduction. DDECS (2013)
Daniel Arbet, Gábor Gyepes, Juraj Brenkus, Viera Stopjaková
OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filters. DDECS (2012)
Gábor Gyepes, Daniel Arbet, Juraj Brenkus, Viera Stopjaková
Application of IDDT test towards increasing SRAM reliability in nanometer technologies. DDECS (2012)
Daniel Arbet, Juraj Brenkus, Gábor Gyepes, Viera Stopjaková
Increasing the efficiency of analog OBIST using on-chip compensation of technology variations. DDECS (2011)
Gábor Gyepes, Juraj Brenkus, Daniel Arbet, Viera Stopjaková
Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies. DDECS (2011)
Juraj Brenkus, Viera Stopjaková, Ronny Vanhooren, Anton Chichkov
Comparison of different test strategies on a mixed-signal circuit. DDECS (2009)
Juraj Brenkus, Viera Stopjaková, Jozef Mihálov
Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation. DDECS (2008)