Lukás Nagy

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 33

Top Topics

Cmos Technology

Top Venues

J. Circuits Syst. Comput.

Publications

Lukás Nagy, Michal Sovcik, Viera Stopjaková
Design of Ultra-Low Power Comparator in 65 NM CMOS Technology with Rail-to-Rail Input Range. AFRICON (2023)
Daniel Arbet, Martin Kovác, David Maljas, Lukás Nagy, Viera Stopjaková
High Power Supply Rejection LDO Regulator for Switching Applications. MIPRO (2022)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková
Low-Power Rail-to-Rail Comparator in 130 nm CMOS Technology. RADIOELEKTRONIKA (2022)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Róbert Ondica, Viera Stopjaková
EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method. AFRICON (2021)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková
EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design. DDECS (2021)
Daniel Arbet, Miroslav Potocný, Martin Kovác, Lukás Nagy, Viera Stopjaková
Fully On-Chip Low-Drop Regulator for Low-Power Applications. MIPRO (2021)
Miroslav Potocný, Martin Kovác, Daniel Arbet, Michal Sovcik, Lukás Nagy, Viera Stopjaková, Richard Ravasz
Low-Voltage DC-DC Converter for IoT and On-Chip Energy Harvester Applications. Sensors 21 (17) (2021)
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems. CoRR (2021)
Adam Hudec, Lukás Nagy, Martin Kovác, Viera Stopjaková
Maximum Power Point Tracking Circuit for an Energy Harvester in 130 nm CMOS Technology. CoRR (2021)
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems. MECO (2020)
Lukás Nagy, Ales Chvála, Viera Stopjaková
Low-Leakage ESD Structures in 130nm CMOS Technology. RADIOELEKTRONIKA (2020)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková
Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology. DDECS (2020)
Martin Kovác, Daniel Arbet, Lukás Nagy, Michal Sovcik, Viera Stopjaková
Multi-Topology DC-DC Converter for Low-Voltage Energy Harvesting Systems. MIPRO (2020)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková
Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS Technology. DDECS (2019)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková
Performance Analysis Of Ultra Low-Voltage Rail-to-Rail Comparator In 130 nm CMOS Technology. AFRICON (2019)
Ales Chvála, Lukás Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Satka, Michal Blaho, Dagmar Gregusová, Ján Kuzmík
Device and Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Cells Comprising D- and E-Mode HEMTs. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Martin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy
Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design Methodology. DDECS (2019)
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
A Novel On-Chip Task Scheduler for Mixed-Criticality Real-Time Systems. J. Circuits Syst. Comput. 28 (Supplement-1) (2019)
Ales Chvála, Lukás Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Satka
Neural Network for Circuit Models of Monolithic InAlN/GaN NAND and NOR Logic Gates. DTIS (2019)
Viera Stopjaková, Martin Kovác, Daniel Arbet, Lukás Nagy
Towards Energy-autonomous Integrated Systems Through Ultra-low Voltage Analog IC Design. MIXDES (2019)
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality Systems. DDECS (2019)
Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Michal Sovcik
Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications. DDECS (2018)
Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková
Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology. DDECS (2018)
Ales Chvála, Lukás Nagy, Juraj Marek, Juraj Priesol, Daniel Donoval, Alexander Satka, Michal Blaho, Dagmar Gregusová, Ján Kuzmík
Device and circuit models of InAlN/GaN D- and dual-gate E-mode HEMTs for design and characterisation of monolithic NAND logic cell. DTIS (2018)
Lukás Kohútka, Lukás Nagy, Viera Stopjaková
A Novel Hardware-Accelerated Priority Queue for Real-Time Systems. DSD (2018)
Juraj Brenkus, Viera Stopjaková, Viera Cernanová, Daniel Arbet, Lukás Nagy, Vladimír Sedlák
A Novel Method Towards Time-Efficient Fault Analysis of Analog and Mixed-Signal Circuits. J. Circuits Syst. Comput. 26 (8) (2017)
Daniel Arbet, Viera Stopjaková, Martin Kovác, Lukás Nagy, Matej Rakus, Michal Sovcik
130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications. J. Circuits Syst. Comput. 26 (8) (2017)
Lukás Nagy, Daniel Arbet, Martin Kovác, Viera Stopjaková
Low-power bulk-driven rail-to-rail comparator in 130 nm CMOS technology. AFRICON (2017)
Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Juraj Brenkus
Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology. DDECS (2016)
Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Michal Sovcik
Variable-gain amplifier for ultra-low voltage applications in 130nm CMOS technology. MIPRO (2016)
Juraj Brenkus, Viera Stopjaková, Lukás Nagy, Daniel Arbet
Impedance calculation based method for AC fault analysis of mixed-signal circuits. DDECS (2016)
Lukás Nagy, Viera Stopjaková, Alexander Satka
Design of In AlN/GaN Heterostructure-Based Logic Cells. DDECS (2015)
Daniel Arbet, Gabriel Nagy, Martin Kovác, Viera Stopjaková, Lukás Nagy
Readout interface for capacitive MEMS microphone in CMOS technology. MIXDES (2015)
Roman Záluský, Daniela Durackova, Viera Stopjaková, Lukás Nagy, Vladimír Sedlák
Novel architecture of a digital neuron for FFNN employing special multiplication. ECAI (2014)
Ales Chvála, Daniel Donoval, Lukás Nagy, Juraj Marek, Patrik Pribytny, Marian Molnar
3-D electrothermal device/circuit simulation of DC-DC converter module in multi-die IC. ESSDERC (2014)
Lukás Nagy, Viera Stopjaková, Juraj Brenkus
Current Sensing Completion Detection in Single-Rail Asynchronous Systems. Comput. Informatics 33 (5) (2014)
Lukás Nagy, Viera Stopjaková, Roman Záluský
Completion detection in dual-rail asynchronous systems by current-sensing. Microelectron. J. 44 (6) (2013)
Lukás Nagy, Viera Stopjaková
Current sensing completion detection in dual-rail asynchronous systems. DDECS (2012)
Lukás Nagy, Viera Stopjaková
Current sensing methodology for completion detection in self-timed systems. DDECS (2011)
Lukás Nagy, Viera Stopjaková
Current Sensing Completion Detection in deep sub-micron technologies. DDECS (2010)