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Dynamic Properties Of Ultra Low-Voltage Rail-to-Rail Comparator Designed In 130 nm CMOS Technology.
Lukás Nagy
Daniel Arbet
Martin Kovác
Miroslav Potocný
Michal Sovcik
Viera Stopjaková
Published in:
DDECS (2020)
Keyphrases
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cmos technology
low voltage
high speed
low power
power line
power consumption
parallel processing
image sensor
leakage current
low cost
random access memory
power dissipation
real time
mixed signal
computer vision
image formation
digital signal processing
design considerations
digital camera
image processing