Juan José Raygoza-Panduro

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 3

Top Topics

Nonlinear Systems

Hardware Implementation

Image Filtering

Geometric Algebra

Top Venues

IEEE Embed. Syst. Lett.

Comput. Appl. Eng. Educ.

Publications

Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, Luis Pizano-Escalante, Juan José Raygoza-Panduro
Vector Accelerator Unit for Caravel. IEEE Embed. Syst. Lett. 16 (1) (2024)
L. A. Luna-Rodriguez, F. J. Rodriguez-Navarrete, Susana Ortega-Cisneros, Miguel Rivera-Acosta, Jorge Rivera Dominguez, Juan José Raygoza-Panduro
Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface. CCE (2022)
Emmanuel Dávila Delgado, Juan José Raygoza-Panduro, Edwin C. Becerra-Alvarez, Francisco Javier Espinoza Jurado, Eric Francisco Gutiérrez Frías
Low cost DSP-based educational embedded platform for real-time simulation and fast implementation of complex systems in Simulink. Comput. Appl. Eng. Educ. 27 (4) (2019)
Jorge Rivera, Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Andrés Figueroa, Ofelia Begovich
FPGA-based startup for AC electric drives: Application to a greenhouse ventilation system. Comput. Ind. 74 (2015)
Susana Ortega-Cisneros, Jorge Rivera Dominguez, Pablo Moreno Villalobos, Carlos Agustin Torres C., H. Hernandez-Hector, Juan José Raygoza-Panduro
An image processor for convolution and correlation of binary images implemented in FPGA. CCE (2015)
Susana Ortega-Cisneros, Miguel A. Carrazco-Díaz, Adrian Pedroza de-la-Crúz, Juan José Raygoza-Panduro, Jorge Rivera Dominguez, Federico Sandoval-Ibarra
HW/SW Co-Design of a Specific Accelerator for Robotic Computer Vision. Computación y Sistemas 19 (3) (2015)
Gerardo Soria García, Adrian Pedroza de-la-Crúz, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Eduardo Bayro-Corrochano
A Hardware Implementation of a Unit for Geometric Algebra Operations With Parallel Memory Arrays (Abstract Only). FPGA (2015)
Susana Ortega-Cisneros, Juan Luis del Valle-Padilla, Ivan Emmanuel Duenas Garcia, Jorge Rivera Dominguez, Juan José Raygoza-Panduro
Design and implementation of a DC motor control using Field Programmable Analog Arrays. CCE (2015)
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, José Roberto Reyes Barón, Daniel Tonali Aranda Bretón, Antonio Casillas Zamora
Characterization technique to implement self-timed cells for VLSI design blocks. CCE (2014)
J. A. Rentería-Cedano, L. M. Aguilar-Lobo, Susana Ortega-Cisneros, José Raúl Loo-Yau, Juan José Raygoza-Panduro
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems. CIARP (2014)
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Daniel Tonali Aranda Bretón, José Roberto Reyes Barón
Space-time AER protocol receiver asynchronously controlled on FPGA. CCE (2014)
Susana Ortega-Cisneros, Miguel A. Carrazco-Díaz, Adrian Pedroza de-la-Crúz, Juan José Raygoza-Panduro, Federico Sandoval-Ibarra, Jorge Rivera Dominguez
Real Time Hardware Accelerator for Image Filtering. CIARP (2014)
Jorge Rivera, Florentino Chavira, Alexander G. Loukianov, Susana Ortega-Cisneros, Juan José Raygoza-Panduro
Discrete-time modeling and control of a boost converter by means of a variational integrator and sliding modes. J. Frankl. Inst. 351 (1) (2014)
Jorge Rivera, Christian Mora-Soto, Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alexander G. Loukianov
Copper and Core Loss Minimization for Induction Motors Using High-Order Sliding-Mode Control. IEEE Trans. Ind. Electron. 59 (7) (2012)
Alexander G. Loukianov, Jorge Rivera, Alma Y. Alanis, Juan José Raygoza-Panduro
Super-twisting sensorless control of linear induction motors. CCE (2012)
Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Jorge Rivera, Alberto de la Mora Gálvez
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System. Int. J. Reconfigurable Comput. 2008 (2008)
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Alberto de la Mora Gálvez
Design and Implementation of the AMCC Self-Timed Microprocessor in FPGAs. J. Univers. Comput. Sci. 13 (3) (2007)
Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo
Rapid prototyping of a self-timed ALU with FPGAs. ReConFig (2005)
Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo
FPGA implementation of a synchronous and self-timed neuroprocessor. ReConFig (2005)