José Raúl Loo-Yau

Publication Activity (10 Years)

Years Active: 2012-2023
Publications (10 Years): 4

Top Topics

Analog Circuits

Fpga Implementation

Nonlinear Systems

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ismary Lavandera-Hernández, José Raúl Loo-Yau, J. Apolinar Reynoso-Hernández, Daniel Ochoa-Armas, Pablo Moreno Villalobos
Frequency-Dependent Design Spaces for Continuous Mode Class-J*/B/J PA. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
C. Perez-Wences, José Raúl Loo-Yau, Pablo Moreno
Simple and Low-Cost Measurement Test Setup to Determine the RF, LO and IF Impedances for Designing GaN FET Resistive Mixer. MWSCAS (2019)
José-Cruz Nuñez Pérez, José Ricardo Cárdenas-Valdez, Katherine Montoya-Villegas, J. Apolinar Reynoso-Hernández, José Raúl Loo-Yau, Christian Gontrand, Esteban Tlelo-Cuautle
FPGA-based test bed for measurement of AM/AM and AM/PM distortion and modeling memory effects in RF PAs. Integr. 52 (2016)
David Martinez, Pablo Moreno, José Raúl Loo-Yau
A new model for non-uniform transmission lines. CCE (2015)
L. M. Aguilar-Lobo, A. Garcia-Osorio, José Raúl Loo-Yau, Susana Ortega-Cisneros, P. Moreno, José Ernesto Rayas-Sánchez, J. Apolinar Reynoso-Hernández
A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers. MWSCAS (2014)
J. A. Rentería-Cedano, L. M. Aguilar-Lobo, Susana Ortega-Cisneros, José Raúl Loo-Yau, Juan José Raygoza-Panduro
FPGA Implementation of a NARX Network for Modeling Nonlinear Systems. CIARP (2014)
J. A. Rentería-Cedano, L. M. Aguilar-Lobo, José Raúl Loo-Yau, Susana Ortega-Cisneros
Implementation of a NARX neural network in a FPGA for modeling the inverse characteristics of power amplifiers. MWSCAS (2014)
A. Garcia-Osorio, José Raúl Loo-Yau, P. Moreno, Luis Ilich Guerrero-Linares, J. Apolinar Reynoso-Hernández
PAs. MWSCAS (2013)
Luis I. Guerrero-Linares, F. Sandoval-Ibarra, José Raúl Loo-Yau
Non-idealities in analog circuits design: What does it really mean? MWSCAS (2012)