José Ernesto Rayas-Sánchez

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 11

Top Topics

Industrial Environment

Power Distribution

Gallium Arsenide

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Aurea Edna Moreno-Mojica, José Ernesto Rayas-Sánchez
Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
José Ernesto Rayas-Sánchez, Francisco E. Rangel-Patino, Benjamin Mercado-Casillas, Felipe de Jesus Leal-Romo, José Luis Chávez-Hurtado
Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks. LASCAS (2020)
Francisco E. Rangel-Patino, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. IEEE Trans. Emerg. Top. Comput. 8 (2) (2020)
Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (4) (2019)
Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez
A tool for the automatic generation and analysis of regular analog layout modules. Integr. 65 (2019)
Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Nagib Hakim
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation. ITC (2018)
Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim
Direct optimization of a PCI express link equalization in industrial post-silicon validation. LATS (2018)
Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez
Jitter tolerance acceleration using the golden section optimization technique. LASCAS (2018)
Ismael Lomeli-Illescas, Sergio A. Solis-Bustos, José Ernesto Rayas-Sánchez
Analysis of the implications of stacked devices in nano-scale technologies for analog applications. LATS (2017)
Felipe de Jesus Leal-Romo, José Ernesto Rayas-Sánchez, Jiangqi He
Design of experiments implementation towards optimization of power distribution networks. LASCAS (2017)
J. Rafael del-Rey, Zabdiel Brito-Brito, José Ernesto Rayas-Sánchez
Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect. LATS (2015)
L. M. Aguilar-Lobo, A. Garcia-Osorio, José Raúl Loo-Yau, Susana Ortega-Cisneros, P. Moreno, José Ernesto Rayas-Sánchez, J. Apolinar Reynoso-Hernández
A digital predistortion technique based on a NARX network to linearize GaN class F power amplifiers. MWSCAS (2014)
José Ernesto Rayas-Sánchez, Zabdiel Brito-Brito, Juan C. Cervantes-González, Carlos A. Lopez
Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures. LASCAS (2013)
José Ernesto Rayas-Sánchez
A frequency-domain approach to interconnect crosstalk simulation and minimization. Microelectron. Reliab. 44 (4) (2004)