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A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.

Francisco E. Rangel-PatinoAndres Viveros-WacherJosé Ernesto Rayas-SánchezIsmael Duron-RosalesEdgar-Andrei Vega-OchoaNagib HakimEnrique Lopez-Miralrio
Published in: IEEE Trans. Emerg. Top. Comput. (2020)
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