FPGA implementation of a synchronous and self-timed neuroprocessor.

Juan José Raygoza-Panduro Susana Ortega-Cisneros Eduardo I. Boemo

Published in: ReConFig (2005)

Keyphrases

neural network
fpga implementation
hardware implementation
low power
high bandwidth
field programmable gate array
multiscale
efficient implementation
image processing algorithms
real time
object oriented
transfer function
asynchronous communication
low cost