Einar J. Aas

Publication Activity (10 Years)

Years Active: 1975-2011
Publications (10 Years): 0

Publications

Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
An Enhanced Path Delay Fault Simulator for Combinational Circuits. DSD (2011)
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
Design of embedded TCAM based longest prefix match search engine. Microprocess. Microsystems 35 (8) (2011)
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef
A programmable BIST with macro and micro codes for embedded SRAMs. EWDTS (2011)
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
Experiments with ABIST test methodology applied to path delay fault testing. EWDTS (2010)
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
Path-Delay Fault Testing in Embedded Content Addressable Memories. DSD (2010)
Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas
Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. ACM Great Lakes Symposium on VLSI (2009)
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. J. Signal Process. Syst. 53 (3) (2008)
Sverre Wichlund, Frank Berntsen, Einar J. Aas
Scan Test Response Compaction Combined with Diagnosis Capabilities. J. Electron. Test. 24 (1-3) (2008)
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas
Probabilistic gate-level power estimation using a novel waveform set method. ACM Great Lakes Symposium on VLSI (2007)
Sverre Wichlund, Frank Berntsen, Einar J. Aas
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. DFT (2006)
Sverre Wichlund, Einar J. Aas
Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory Compactor. ATS (2006)
Øystein Gjermundnes, Einar J. Aas
Remote Path Delay Fault Simulation. DSD (2005)
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Storage requirement estimation for optimized design of data intensive applications. ACM Trans. Design Autom. Electr. Syst. 9 (2) (2004)
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Data dependency size estimation for use in memory optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (7) (2003)
Øyvind Strøm, Kjetil Svarstad, Einar J. Aas
On the Utilization of Java Technology in Embedded Systems. Des. Autom. Embed. Syst. 8 (1) (2003)
Ayman M. Wahba, Einar J. Aas
Formal verification of digital circuits by 3-valued simulation. ICECS (2001)
Øyvind Strøm, Einar J. Aas
An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. DSD (2001)
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. DAC (2001)
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Storage requirement estimation for data intensive applications with partially fixed execution ordering. CODES (2000)
Sverre Wichlund, Einar J. Aas
On efficient CPU-usage in a VLSI CAD-environment with application to circuit partitioning. ICECS (2000)
Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas
Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. ICCAD (2000)
Einar J. Aas
Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. ISQED (2000)
Øyvind Strøm, Audun Klauseie, Einar J. Aas
A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs. EUROMICRO (1999)
Einar J. Aas, Jukka Typpo
Project based learning objectives and experiences in electronic education: a memory controller design experiment. ICECS (1999)
Ingil Sundsbo, G. Lokken Hansen, Einar J. Aas
Comparison of two architectures for implementation of the discrete cosine transform. ICASSP (1996)
Johnny Pihl, Einar J. Aas
4300 Megasamples/s Wave Digital Filter Implementation In Bit-parallel Tspc Circuit Technique. ISSPA (1996)
Einar J. Aas, Tore Steen, Karl Klingsheim
Quantifying Design Quality Through Design Experiments. IEEE Des. Test Comput. 11 (1) (1994)
Ayman M. Wahba, Einar J. Aas
Verification and Diagnosis of Digital Systems by Termary Reasoning. CHARME (1993)
Einar J. Aas, Gunnar Nystu
Experiments with autonomous test of PLAs. EURO-DAC (1991)
Bjørg Reppen, Einar J. Aas
Combined probabilistic testability calculation and compact test generation for PLAs. J. Electron. Test. 2 (3) (1991)
Ove Brynestad, Einar J. Aas, Anne E. Vallestad
State transition graph analysis as a key to BIST fault coverage. ITC (1990)
Dag Svanæs, Einar J. Aas
Test generation through logic programming. Integr. 2 (1) (1984)
Hedayat Markus Bayegan, Einar J. Aas
An integrated system for interactive editing of schematics, logic simulation and PCB layout design. DAC (1978)
P. A. Arneberg, Einar J. Aas
Design automation in norway. DAC (1975)