An Enhanced Path Delay Fault Simulator for Combinational Circuits.
Palanichamy ManikandanBjørn B. LarsenEinar J. AasPublished in: DSD (2011)
Keyphrases
- logic circuits
- power dissipation
- asynchronous circuits
- fault detection
- fault diagnosis
- fault models
- shortest path
- power consumption
- simulation model
- destination node
- path length
- path selection
- high speed
- multicast tree
- analog circuits
- genetic algorithm
- analog vlsi
- tunnel diode
- real time
- path finding
- optimal path
- low power
- test bed
- low cost