Formal verification of digital circuits by 3-valued simulation.

Ayman M. Wahba Einar J. Aas

Published in: ICECS (2001)

Keyphrases

formal verification
digital circuits
model checking
automated verification
model based diagnosis
finite state machines
model checker
bounded model checking
program slicing
symbolic model checking
evolvable hardware
data flow
circuit design
databases
temporal logic
evolutionary algorithm
search algorithm