Basavaraj Talawar

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 31

Top Topics

Network On Chip

Design Space Exploration

Traveling Salesman

Gpu Implementation

Top Venues

J. Circuits Syst. Comput.

Publications

H. D. Kallinatha, Sadhana Rai, Basavaraj Talawar
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment. IEEE Access 12 (2024)
Anil Kumar, Basavaraj Talawar
Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessing. Int. J. Intell. Eng. Informatics 10 (2) (2022)
Anil Kumar, Basavaraj Talawar
LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures. J. Circuits Syst. Comput. 31 (11) (2022)
Pramod Yelmewad, Basavaraj Talawar
Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing Problem. Clust. Comput. 24 (4) (2021)
Pramod Yelmewad, Basavaraj Talawar
Parallel deterministic local search heuristic for minimum latency problem. Clust. Comput. 24 (2) (2021)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
FPGA friendly NoC simulation acceleration framework employing the hard blocks. Computing 103 (8) (2021)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks. Circuits Syst. Signal Process. 39 (10) (2020)
Bheemappa Halavar, Basavaraj Talawar
Power and performance analysis of 3D network-on-chip architectures. Comput. Electr. Eng. 83 (2020)
Anil Kumar, Basavaraj Talawar
ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures. Int. J. Comput. Sci. Eng. 23 (4) (2020)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. Wirel. Pers. Commun. 114 (4) (2020)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA. ACM Trans. Design Autom. Electr. Syst. 25 (1) (2020)
Mishal Shah, Mehnaz Yunus, Pavan Vachhani, Leslie Monis, Mohit P. Tahiliani, Basavaraj Talawar
PowerDPDK: Software-Based Real-Time Power Measurement for DPDK Applications. NFV-SDN (2020)
Pramod Yelmewad, Aniket Kumar, Basavaraj Talawar
MMAS on GPU for Large TSP Instances. ICCCNT (2019)
Aditya K. Kamath, Leslie Monis, A. Tarun Karthik, Basavaraj Talawar
Storage Class Memory: Principles, Problems, and Possibilities. CoRR (2019)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
Analysis of cache behaviour and software optimizations for faster on-chip network simulations. Int. J. Syst. Assur. Eng. Manag. 10 (4) (2019)
Pramod Yelmewad, Basavaraj Talawar
Parallel iterative hill climbing algorithm to solve TSP on GPU. Concurr. Comput. Pract. Exp. 31 (7) (2019)
Bheemappa Halavar, Ujjwal Pasupulety, Basavaraj Talawar
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures. Simul. Model. Pract. Theory 96 (2019)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs. J. Circuits Syst. Comput. 28 (12) (2019)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA. VLSI-DAT (2019)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs. ISQED (2019)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks. VLSI-DAT (2019)
Bheemappa Halavar, Basavaraj Talawar
OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture. ISDA (1) (2018)
Bheemappa Halavar, Basavaraj Talawar
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip. SPCOM (2018)
Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. VLSI Design (2018)
Anil Kumar, Basavaraj Talawar
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks. IC3 (2018)
Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures. ISED (2018)
Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV). ICACCI (2018)
G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. ISED (2018)
Basavaraj Talawar, Pramod Yelmewad
GPU-Based Iterative Hill Climbing Algorithm to Solve Symmetric Traveling Salesman Problem. TopHPC (2017)
Adithya H. K. Upadhya, Basavaraj Talawar, Jeny Rajan
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images. J. Real Time Image Process. 13 (1) (2017)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
Cache analysis and software optimizations for faster on-chip network simulations. ICIIS (2016)
Basavaraj Talawar
A Crossbar Interconnection Network in DNA. IPDPS Workshops (2015)