Khyamling Parane

Publication Activity (10 Years)

Years Active: 2016-2021
Publications (10 Years): 12

Top Topics

Design Space Exploration

Multiprocessor Architecture

Network On Chip

Top Venues

Publications

Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
FPGA friendly NoC simulation acceleration framework employing the hard blocks. Computing 103 (8) (2021)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks. Circuits Syst. Signal Process. 39 (10) (2020)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. Wirel. Pers. Commun. 114 (4) (2020)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA. ACM Trans. Design Autom. Electr. Syst. 25 (1) (2020)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
Analysis of cache behaviour and software optimizations for faster on-chip network simulations. Int. J. Syst. Assur. Eng. Manag. 10 (4) (2019)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs. J. Circuits Syst. Comput. 28 (12) (2019)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA. VLSI-DAT (2019)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs. ISQED (2019)
Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks. VLSI-DAT (2019)
Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. VLSI Design (2018)
G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. ISED (2018)
Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar
Cache analysis and software optimizations for faster on-chip network simulations. ICIIS (2016)