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YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs.
Khyamling Parane
Prabhu B. M. Prasad
Basavaraj Talawar
Published in:
J. Circuits Syst. Comput. (2019)
Keyphrases
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network on chip
routing algorithm
network simulator
packet switched
ad hoc networks
shortest path
routing protocol
simulation model
mobile ad hoc networks
high speed
simulation models
real time
parallel processing
end to end delay
simulation tools