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LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA.
Khyamling Parane
Prabhu B. M. Prasad
Basavaraj Talawar
Published in:
ACM Trans. Design Autom. Electr. Syst. (2020)
Keyphrases
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network on chip
low latency
packet switched
hardware architecture
hardware design
multi processor
routing algorithm
real time
hardware implementation
high speed
efficient implementation
design methodology
wireless sensor networks
network simulator
cmos technology
data transfer
highly efficient
low cost