Ari Paasio

Publication Activity (10 Years)

Years Active: 1994-2020
Publications (10 Years): 8

Top Topics

Welding Process

Heart Rate Variability

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Mika Grönroos, Ari Paasio, Mika Laiho
High-Dynamic-Range Image Reconstruction from Pixel-Level Self-Reset ADC Samples. ISCAS (2020)
Olli Lahdenoja, Tero Säntti, Jonne K. Poikonen, Mika Laiho, Ari Paasio, Joonas Pekkarinen, Antti Salminen
Embedded processing methods for online visual analysis of laser welding. J. Real Time Image Process. 16 (4) (2019)
Tapani Nevalainen, Esteban Ferro, Víctor M. Brea, Paula López, Ari Paasio
Low-Power Regulator for Micro Energy Harvesting Applications. NORCAS (2018)
Mika Grönroos, Tapani Nevalainen, Ari Paasio
Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors. IEEE Trans. Circuits Syst. II Express Briefs (5) (2018)
Mika Grönroos, Ari Paasio
A novel and systematic implementation of thermometer-coded current-mode DAC. ECCTD (2017)
Ari Paasio
Local memory and logic arrangement for ultra-low power array processors. ISCAS (2017)
Mari Grönroos, Tapani Nevalainen, Jonne Poikonen, Ari Paasio
Fast thermopile readout circuit arrangement for array processors. ISCAS (2017)
Ari Paasio
Ultra low-power array processor propagation circuit arrangement. ISCAS (2016)
Ari Paasio
Local asymmetric propagation stopper circuit for asynchronous binary wave computing. ISCAS (2015)
Tero Säntti, Jonne K. Poikonen, Olli Lahdenoja, Mika Laiho, Ari Paasio
Online seam tracking for laser welding with a vision chip and FPGA enabled camera system. ISCAS (2015)
Mojtaba Jafari Tadi, Eero Lehtonen, Tero Koivisto, Mikko Pänkäälä, Ari Paasio, Mika Teräs
Seismocardiography: Toward heart rate variability (HRV) estimation. MeMeA (2015)
Mojtaba Jafari Tadi, Tero Koivisto, Mikko Pänkäälä, Ari Paasio
Accelerometer-Based Method for Extracting Respiratory and Cardiac Gating Information for Dual Gating during Nuclear Medicine Imaging. Int. J. Biomed. Imaging 2014 (2014)
Ari Paasio
CheckerBoard binary CNN core. ISCAS (2014)
Mika Kutila, Ari Paasio, Teijo Lehtonen
Simulations on 130 nm technology 6T SRAM cell for Near-Threshold operation. ISCAS (2014)
Mika Kutila, Ari Paasio, Teijo Lehtonen
Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation. MWSCAS (2014)
Olli Lahdenoja, Tero Säntti, Mika Laiho, Ari Paasio, Jonne K. Poikonen
Seam tracking with adaptive image capture for fine-tuning of a high power laser welding process. ICMV (2014)
Olli Lahdenoja, Tero Säntti, Jonne Poikonen, Mika Laiho, Ari Paasio
Characterizing Spatters in Laser Welding of Thick Steel Using Motion Flow Analysis. SCIA (2013)
Ari Paasio
Prototype rotation based assisted image analysis for 3D vision system. ISCAS (2011)
Jia Sun, Hao Meng, Ari Paasio
Design Techniques and Considerations for a 1.2V 10bit CMOS Pipeline ADC. UKSim (2011)
Hao Meng, Ari Paasio, Jia Sun
A capacitor mismatch insensitive technique for RSD cyclic ADC. ECCTD (2011)
Lauri Koskinen, Jonne Poikonen, Mika Laiho, Ari Paasio
Rate-distortion performance analysis of an analog motion estimation array. ICASSP (2010)
Jonne Poikonen, Mika Laiho, Ari Paasio, Lauri Koskinen, Kari Halonen
An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation. EURASIP J. Adv. Signal Process. 2009 (2009)
Mika Laiho, Jonne Poikonen, Ari Paasio
Space-dependent binary image processing within a 64x64 mixed-mode array processor. ECCTD (2009)
Joona Marku, Jonne Poikonen, Ari Paasio
Temperature Compensation in Combination Selection based Mismatch Calibration. ISCAS (2009)
Joona Marku, Jonne Poikonen, Ari Paasio
Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technology. SoCC (2009)
Mika Laiho, Víctor M. Brea, Ari Paasio
Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2009)
Jonne Poikonen, Mika Laiho, Ari Paasio
MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array. ISCAS (2009)
Olli Lahdenoja, Mika Laiho, Ari Paasio
On the Spatial Distribution of Local Non-parametric Facial Shape Descriptors. SCIA (2009)
Mika Laiho, Jonne Poikonen, Peter Virta, Ari Paasio
Live Demonstration: MIPA4k: A 64×64 Cell Mixed-mode Image Processor Array. ISCAS (2009)
Jonne Poikonen, Mika Laiho, Ari Paasio
Locally adaptive image sensing with the 64x64 cell MIPA4k mixed-mode image processor array. ECCTD (2009)
Jonne Poikonen, Ari Paasio
An 8times 8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-muhboxm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Janne Maunu, Mika Laiho, Tero Koivisto, Kati Virtanen, Mikko Pänkäälä, Ari Paasio
Mixed-signal baseband processing chain for a MB-OFDM receiver. ICECS (2008)
Mika Laiho, Jonne Poikonen, Ari Paasio, Kari Halonen
Centroiding and classification of objects using a processor array with a scalable region of interest. ISCAS (2008)
Janne Maunu, Mika Laiho, Ari Paasio
A Differential Architecture for an Online Analog Viterbi Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2008)
Mika Laiho, Ari Paasio, Jacek Flak, Kari Halonen
Template Design for Cellular Nonlinear Networks With 1-Bit Weights. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2008)
Olli Lahdenoja, Mika Laiho, Janne Maunu, Ari Paasio
A Massively Parallel Face Recognition System. EURASIP J. Embed. Syst. 2007 (2007)
Lauri Koskinen, Ari Paasio, Kari Halonen
CNN-type algorithms for H.264 variable block-size partitioning. Signal Process. Image Commun. 22 (9) (2007)
Lauri Koskinen, Joona Marku, Ari Paasio, Kari Halonen
Architecture for Analog Variable Block-Size Motion Estimation. ICIP (2) (2007)
Víctor M. Brea, Mika Laiho, Natalia A. Fernandez-Garcia, Ari Paasio, Diego Cabello
Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models. ECCTD (2007)
Kati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio
A 12-bit Current-Steering DAC with Calibration by Combination Selection. ISCAS (2007)
Olli Lahdenoja, Janne Maunu, Mika Laiho, Ari Paasio
A massively parallel algorithm for local binary pattern based face recognition. ISCAS (2006)
Janne Maunu, Mikko Pänkäälä, Joona Marku, Jonne Poikonen, Mika Laiho, Ari Paasio
Current source calibration by combination selection of minimum sized devices. ISCAS (2006)
Mikko Pänkäälä, Kati Virtanen, Ari Paasio
An Analog 2-D DCT Processor. IEEE Trans. Circuits Syst. Video Technol. 16 (10) (2006)
Janne Maunu, Joona Marku, Mika Laiho, Ari Paasio
An On-Chip Measurement Circuit for Calibration by Combination Selection. SoCC (2006)
Olli Lahdenoja, Esa Alhoniemi, Mika Laiho, Ari Paasio
A Shape-Preserving Non-parametric Symmetry Transform. ICPR (2) (2006)
Tero Koivisto, Teemu Peltonen, Meigen Shen, Esa Tjukanoff, Ari Paasio
Sine wave as a correlating signal for UWB radio. ISCAS (2006)
Jonne Poikonen, Ari Paasio
On the topographic equivalence between voltage mode and current mode ranked order filters for array processors. ISCAS (2006)
Jacek Flak, Mika Laiho, Ari Paasio, Kari Halonen
Dense CMOS implementation of a binary-programmable cellular neural network. Int. J. Circuit Theory Appl. 34 (4) (2006)
Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello
A binary-based on-chip CNN solution for pixel-level snakes. Int. J. Circuit Theory Appl. 34 (4) (2006)
Kati Virtanen, Mikko Pänkäälä, Mika Laiho, Ari Paasio
Implementation of an asynchronous current-mode ADC with adaptive quantization. ISCAS (2006)
Mika Laiho, Ari Paasio, Víctor M. Brea
Effect of mismatch on the reliability of binary-programmable CNNs. ISCAS (2006)
Kati Virtanen, N. Pankaala, Ari Paasio
Compensation of errors generated by an analog 2D DCT. ISCAS (6) (2005)
Lauri Koskinen, Ari Paasio, Kari Halonen
Motion estimation computational complexity reduction with CNN shape segmentation. IEEE Trans. Circuits Syst. Video Technol. 15 (6) (2005)
Mika Laiho, Ari Paasio, Jacek Flak, Kari Halonen
Template design for binary-programmable cellular nonlinear networks. ISCAS (4) (2005)
Olli Lahdenoja, Mika Laiho, Ari Paasio
Reducing the feature vector length in local binary pattern based face recognition. ICIP (2) (2005)
Víctor M. Brea, Mika Laiho, Ari Paasio
Robustness improvement in binary cellular non-linear network architectures. ECCTD (2005)
Asko Kananen, Ari Paasio, Kari Halonen
A simple variable λ resistive network implementation. ECCTD (2005)
Olli Lahdenoja, Jonne Poikonen, Ari Paasio
Effect of mismatch on a ranked-order extractor array [image processing applications]. ISCAS (4) (2005)
Laura Vesalainen, Jonne Poikonen, Ari Paasio
A Gray-coded digital-to-analog converter for a mixed-mode processor array. ISCAS (4) (2005)
Lauri Koskinen, Kari Halonen, Ari Paasio
Parallel processor algorithm for variable block-size computation at low bitrates [video coding applications]. ISCAS (4) (2005)
Mika Laiho, Ari Paasio
Dynamically coupled multi-layer mixed-mode CNN. ISCAS (6) (2005)
Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello
A one-quadrant discrete-time cellular neural network architecture for pixel-level snakes: B/W processing. ISCAS (4) (2005)
Jonne Poikonen, Ari Paasio
Rank identification for an analog ranked order filter. ISCAS (3) (2005)
Kati Virtanen, Mikko Pänkäälä, Ari Paasio
A current-mode ADC with adaptive quantization. ISCAS (4) (2005)
Víctor M. Brea, Mika Laiho, David López Vilariño, Ari Paasio, Diego Cabello
A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes. ISCAS (6) (2005)
Ari Paasio, Jacek Flak, Mika Laiho, Kari Halonen
High density VLSI implementation of a bipolar CNN with reduced programmability. ISCAS (3) (2004)
Laura Vesalainen, Jonne Poikonen, Mikko Pänkäälä, Ari Paasio
A gray-code current-mode ADC for mixed-mode cellular computer. ISCAS (3) (2004)
Asko Kananen, Mika Laiho, Kari Halonen, Ari Paasio
N × 16 cellular test chips for low-pass filtering large images. ISCAS (5) (2004)
Víctor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello
Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2004)
Jonne Poikonen, Ari Paasio
A ranked order filter implementation for parallel analog processing. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2004)
Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
A mixed-mode polynomial cellular array processor hardware realization. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2004)
Mikko Pänkäälä, Jonne Poikonen, Laura Vesalainen, Ari Paasio
Realization of an analog current-mode 2D DCT. ISCAS (1) (2004)
Lauri Koskinen, Ari Paasio, Kari Halonen
3-neighborhood motion estimation in CNN silicon architectures. ISCAS (5) (2004)
Mika Laiho, Ari Paasio, Kari Halonen
Improved cell core for a mixed-mode polynomial CNN. ISCAS (3) (2004)
Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
Realization of Couplings in a Polynomial Type Mixed-Mode Cellular Neural Network. Int. J. Neural Syst. 13 (6) (2003)
Lauri Koskinen, Ari Paasio, Kari Halonen
CNN shape segmentation advantages in MPEG-4 simple profile encoding. ISSPA (2) (2003)
Ari Paasio, Mika Laiho, Asko Kananen, Kari Halonen, Jonne Poikonen
A 32×32 cellular test chip targeting new functionalities. ISCAS (3) (2003)
Jonne Poikonen, Ari Paasio
An area-efficient full-wave current rectifier for analog array processing. ISCAS (5) (2003)
Víctor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello
Implementation oriented theory design issues on the DTCNN template generation. ISCAS (3) (2002)
Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
Cell and network level design of a mixed-mode CNN. ISCAS (1) (2002)
Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
A mixed-mode polynomial-type CNN for analysing brain electrical activity in epilepsy. Int. J. Circuit Theory Appl. 30 (2-3) (2002)
Lauri Koskinen, Ari Paasio, Mika Laiho, Kari Halonen
Effect of CNN shape segmentation on MPEG-4 shape bit-rate. ISCAS (4) (2002)
Asko Kananen, Ari Paasio, Mika Laiho, Kari Halonen
CNN applications from the hardware point of view: video sequence segmentation. Int. J. Circuit Theory Appl. 30 (2-3) (2002)
Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
Discrete time analog polynomial type CNN with digital state. ISCAS (3) (2001)
Ari Paasio, Jani Paakkulainen, Jouni Isoaho
A multiplier-free fixed-task digital CNN array for video segmentation system. ISCAS (2000)
Mika Laiho, Ari Paasio, Kari Halonen
Building blocks for large annealed compact neural networks. ISCAS (2000)
Ari Paasio, Asko Kananen, Kari Halonen, Veikko Porra
A QCIF Resolution Binary I/O CNN-UM Chip. J. VLSI Signal Process. 23 (2-3) (1999)
Ari Paasio, Adam Dawidziuk
CNN template robustness with different output nonlinearities. Int. J. Circuit Theory Appl. 27 (1) (1999)
Ari Paasio, Asko Kananen, Kari Halonen
Very fast and compact fixed template CNN realizations for B/W processing. ISCAS (5) (1999)
Ari Paasio, Asko Kananen, Kari Halonen, Veikko Porra
A 48 by 48 CNN chip operating with B/W images. ICECS (1998)
Ari Paasio, Adam Dawidziuk, Veikko Porra
Implementation of cellular neural network operating with bipolar images. ICNN (1996)
Ari Paasio, Adam Dawidziuk, Veikko Porra
VLSI implementation of cellular neural network universal machine. ICECS (1996)
Ari Paasio, Kari Halonen, Veikko Porra
CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template Coefficients. ISCAS (1994)