Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors.
Mika GrönroosTapani NevalainenAri PaasioPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2018)
Keyphrases
- low power
- cmos technology
- high speed
- signal processor
- power consumption
- power reduction
- logic circuits
- low cost
- image sensor
- single chip
- vlsi architecture
- power dissipation
- vlsi circuits
- high power
- gate array
- parallel processing
- digital signal processing
- low voltage
- low power consumption
- delay insensitive
- mixed signal
- wireless transmission
- ultra low power
- circuit design
- signal processing
- focal plane
- efficient implementation
- parallel implementation
- wide dynamic range
- general purpose
- parallel architecture
- shared memory