Arghavan Asad

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 26

Top Topics

Optimization Model

Memory Subsystem

Top Venues

Publications

Rupinder Kaur, Arghavan Asad, Farah A. Mohammadi
A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Comput. 13 (7) (2024)
Arghavan Asad, Farah A. Mohammadi
Godiva: green on-chip interconnection for DNNs. J. Supercomput. 79 (3) (2023)
Arghavan Asad, Rupinder Kaur, Farah Mohammadi
A Survey on Memory Subsystems for Deep Neural Network Accelerators. Future Internet 14 (5) (2022)
Arghavan Asad, Rupinder Kaur, Farah A. Mohammadi
Noise Suppression Using Gated Recurrent Units and Nearest Neighbor Filtering. CSCI (2022)
Arghavan Asad, Farah A. Mohammadi
NeuroTower: A 3D Neuromorphic Architecture with Low-Power TSVs. FTC (3) (2022)
Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression. CoRR (2022)
Furat Al-Obaidy, Arghavan Asad, Farah A. Mohammadi
A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique. Int. J. Parallel Program. 49 (3) (2021)
Arghavan Asad, Furat Al-Obaidy, Farah Mohammadi
Efficient Power Consumption using Hybrid Emerging Memory Technology for 3D CMPs. LASCAS (2020)
Salman Onsori, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy
An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors. CoRR (2019)
Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi
Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors. CCECE (2019)
Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi
Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method. CCECE (2019)
Arghavan Asad, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, Farah Mohammadi
An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors. J. Circuits Syst. Comput. 28 (13) (2019)
Arghavan Asad, Aniseh Dorostkar, Farah Mohammadi
A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age. EURASIP J. Embed. Syst. 2018 (1) (2018)
Pooneh Safayenikoo, Arghavan Asad, Farah Mohammadi
An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses. CCECE (2018)
Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines. ISCAS (2018)
Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
Optimization-based reconfigurable approach for low-power 3D chip-multiprocessors. LASCAS (2018)
Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors. DSD (2017)
Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors. ISQED (2017)
Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs. CCECE (2017)
Arghavan Asad, Ozcan Ozturk, Mahmood Fathy, Mohammad Reza Jahed-Motlagh
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy. Microprocess. Microsystems 51 (2017)
Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy, Farah Mohammadi
A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors. CCECE (2017)
Fatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli, Mahmood Fathy, Farah Mohammadi
Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure. MCSoC (2017)
Fatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli, Mahmood Fathy, Farah Mohammadi
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors. ReCoSoC (2017)
Arghavan Asad, Mahmood Fathy, Mohammad Reza Jahed-Motlagh, Kaamran Raahemifar
Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach. J. Low Power Electron. 13 (2) (2017)
Pooneh Safayenikoo, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk. NoCArc@MICRO (2016)
Salman Onsori, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model. ISCAS (2016)
Arghavan Asad, Ozcan Ozturk, Mahmood Fathy, Mohammad Reza Jahed-Motlagh
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors. DSD (2015)
Sobhan Niknam, Arghavan Asad, Mahmood Fathy, Amir-Mohammad Rahmani
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. ReCoSoC (2015)
Salman Onsori, Arghavan Asad, Özcan Özturk, Mahmood Fathy
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach. IGSC (2015)
Ashkan Sadeghi, Kaamran Raahemifar, Mahmood Fathy, Arghavan Asad
Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy. MCSoC (2015)
Asghar Keshtkar, Amir Maghoul, Ali Kalantarnia, Arghavan Asad
Design considerations to affect on shielding effectiveness for conductive enclosure. IEICE Electron. Express 8 (13) (2011)
Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi
A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. DSD (2009)
Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. ReConFig (2009)