Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method.
Furat Al-ObaidyArghavan AsadFarah MohammadiPublished in: CCECE (2019)
Keyphrases
- optimization method
- memory subsystem
- multithreading
- embedded processors
- single chip
- low cost
- processor core
- optimization algorithm
- optimization methods
- memory access
- simulated annealing
- particle swarm
- differential evolution
- global optimum
- optimization procedure
- evolutionary algorithm
- optimization process
- genetic algorithm
- nelder mead simplex
- nonlinear optimization
- parallel computing
- high speed
- memory hierarchy
- ibm zenterprise
- parallel algorithm
- metaheuristic
- parallel processing
- main memory
- functional units
- multiprocessor systems
- cost function
- data access
- convex sets
- power consumption
- memory bandwidth
- search algorithm
- shared memory
- optimal solution
- neural network
- low power